The present invention generally relates to the fabrication of organic substrates used in packaging integrated circuits (IC's), and more specifically relates to a method of creating a photo-resist unto the surface of a conductive plane during substrate fabrication.
The substrate of a typical IC package consists of one or more layers of metal circuitry bonded onto insulating or dielectric material. The dielectric base material is typically made from resins such as bismaleimide triazine (BT), cyanate esters, glass-reinforced epoxy or polyimides. These substrates provide mechanical support as well as electrical interconnection for the integrated circuit (IC) chip to one or more external devices.
Packaging substrates are typically manufactured in a series of mechanical and chemical steps, and often includes drilling, photo-imaging, electroless/electrolytic plating, etching, screen printing, routing and punching, and electrical/optical testing. Additional operations are required to manufacture multilayer boards in order to define and etch internal circuitry on thin laminates. These are then stacked and laminated or bonded into a multilayer structure.
To form an image or copper pattern onto the insulating or dielectric material, either “subtractive” or “additive” technology is typically used. Both technologies require the use of an ultraviolet (UV) light sensitive photo-resist to “mask” areas of concern. With subtractive technology, the use of copper-clad laminates necessitates the removal of copper in those regions where it is not wanted to form the copper routing or traces, and the required copper image is masked or covered by the photo-resist so that the “unwanted” areas can be subsequently etched away. FIG. 1 illustrates the steps performed in such a process. On the other hand, additive technology provides that unclad material is used, and copper is electrolessly added only where it is needed.
As shown in FIG. 1, a conductive film 10, such as copper film, is bonded to a dielectric substrate 12. Then, the copper surface is flooded with a photo-resist 14, where the photo-resist material is either in liquid form or is in the form of a dry film. Then, a photomask is generated, where the photomask is usually a stiff glass or a film containing the image of the spaces between the copper traces (hence the often-used term “negative image” of the substrate design). The photomask 16 is then aligned and pressed onto the photo-resist 14 while an ultraviolet light (represented by arrow 18) is beaming on the other side of the mask. Since the photomask 16 contains the opaque metallic image of the spaces between the copper traces, UV light is blocked or reflected back on those areas. On the other hand, UV light passes through the unmasked areas, penetrating and curing the photo-resist underneath the photo-mask. After this process, there are effectively two areas on the photo-resist, one that is exposed 11 or hardened, and the other which is unexposed 13 or uncured. A developing process then removes the unexposed photo-resist which in turn exposes the “unwanted” copper underneath. The “unwanted” copper 22 is then etched away chemically. The last major step of such a method of generating the copper pattern is a photo-resist etch back step where all the hardened photo-resist is removed or cleaned, leaving only the “wanted” copper patterns 10.
As such, the prior art process of forming a copper pattern or image on a dielectric substrate includes many steps, including steps such as masking, exposing the surface to UV light and developing. Additionally, state of the art equipment for practicing such a method is expensive, and conventional methods of applying a thin photo-resist often results in unstable etching quality. Furthermore, the wider width or space decreases the package available I/O, and productivity and/or quality is impacted.